VLSI hardware modules designed to be used in a variety of products have become increasingly important as the complexity and cost of designing complex products has increased. Texas Instruments has recently labeled such modules as generic engineering modules (GEM). In these modules there are multiple clock domains allowing for operation of various parts of the chip at frequencies optimized for speed and power dissipation trade-off. Multiple clocks entering a GEM megamodule, although synchronous to each other, can cause on-chip variations (OCV) also known as clock skew.
Clock dividers used to generate the optimized frequency clock signals typically reside as separate hardware blocks adjacent to a centrally located phase-locked loop (PLL). This commonly used technique establishes tight control over the occurrence of clock edges at multiple frequencies. These clock dividers issue clocks to the various domains within the GEM. The GEM is subject to OCV issues having to do with clock balancing (skew reduction) and static-timing analysis (STA) closure difficulties.
FIG. 1 illustrates a typical prior art design using multiple frequency clocks that are either the PLL clock frequency or a sub-multiple of the PLL clock frequency. Four possible clocks are shown in FIG. 1 and are described below.
In prior art, clock dividers 112, 113 and 114 often reside at a central location near the PLL and within the megamodule. These dividers generate sub-multiple frequency clocks supplementing the highest speed clock coming directly from PLL 101 via delay element 102. Normally one or more clocks generated by dividing the PLL clock down to sub-multiples of the PLL clock are needed to optimize the design for speed and power dissipation. Test clock input (TCK) 131 allows use of test clock to be substituted for the free-running PLL-based clocks during test operations. FIG. 1 illustrates PLL clock and three sub-multiple clocks. These are: PLL frequency clock 121; PLL frequency divided by two clock 122; PLL frequency divided by three clock 123; and PLL frequency divided by four clock 124.
Synchronization of these clocks is controlled by signals from outside the GEM, which guarantees that each clock starts at the identical time. FIG. 4 shows possible non-synchronous clocks that are possible when simple frequency division is implemented. Because the clocks reside physically inside GEM, it is straightforward to control the required clock enables for three different clocking modes: internal clock; external clock; and design-for-test (DFT).
FIG. 1 also illustrates sub-module 150 accepting divide-by-two clock 122 and sub-module 156 accepting divide-by-four clock 124. Delay element 132 provides a delayed version of clock 122 for clocked elements 151 and 152. Delay element 134 provides a delayed version of clock 124 for clocked elements 154 and 155. Delay elements 130 through 134 inject supplemental delays in their respective clock paths allowing additional minor adjustment to establish the timing balance between sub-modules. Possible paths for the PLL frequency clock with delay element 130 and divide-by-three clock divider 113 with delay element 133 are shown as unused in this example.